1. Field of the Invention
The present invention relates to a disk apparatus, and, more particularly, to a disk apparatus which is suitable to constitute a zone-recording disk apparatus.
2. Description of the Related Art
As shown in FIG. 1, a conventional zone-recording disk recording/reproducing apparatus includes, as its recording medium, a magnetic disk recording/reproducing 1 which comprises, for example, a hard disk. The magnetic disk 1 has a recording surface which are sectioned into a first recording zone ZN1, which is the outer zone in the radial direction, and a second recording zone ZN2, which are the inner zone in the same direction. Furthermore, the data recording/reproducing speed to and from the first recording zone ZN1 is arranged to be faster than that to and from the second recording zone ZN2. As a result, the recording density in the first recording zone ZN1 can be made to be substantially the same as that in the second recording zone ZN2. Consequently, the overall recording capacity of the magnetic disk 1 can be enlarged.
The magnetic disk 1 is arranged in such a manner that it can be rotated at a speed of a constant angular velocity, causing the liner velocity of the recording tracks included in the first recording zone ZN1 to be faster than that of the recording tracks included in the second recording zone ZN2. Therefore, if the zone recording system is not employed, the recording density in the first recording zone ZN1, which is the outer zone, is lower than that in the second recording zone ZN2, which is the inner zone. In consequence, the poor recording efficiency results.
However, the conventional disk apparatus has been arranged to comprise a synchronizing signal processing circuit 10 constituted as shown in FIG. 2 or 3. Circuit 10 is used in order to obtain a synchronizing signal with which the data processing speed can be controlled when data is recorded/reproduced to and from the first or the second recording zone ZN1 or ZN2, respectively, in the recording mode or the reproducing mode.
The synchronizing signal processing circuit 10 shown in FIG. 2 comprises a first and second crystal oscillation circuits 11 and 12. Frequency signals S11 and S12 of frequencies f.sub.1 and f.sub.2, which are respectively determined by crystal 11X and crystal 12X, are selectively switched by a switch circuit 13 in response to a zone detection signal S13. The frequency signals S11 and S12 correspond respectively to the data processing speed of the first and second recording zones ZN1 and ZN2. The thus selectively switched frequency signals S11 and S12 are, as reference clock signal S14, transmitted to a data synchronizer 14. As a result, a recording synchronizing clock signal S15, which corresponds either to the first recording zone ZN1 or to the second recording zone ZN2, is transmitted from the data synchronizer 14 in the recording mode.
In the reproducing mode, a reproducing pulse signal S16 transmitted from a reproducing signal processing circuit is received by the data synchronizer 14. A reproducing synchronizing clock signal S17 the frequency of which corresponds to the frequency of the above-described reproducing pulse signal S16 is transmitted from the data synchronizer 14.
In a case where the synchronizing signal processing circuit 10 is structured as shown in FIG. 2, the two crystal oscillating circuits 11 and 12 must be provided as signal generating sources for generating the recording synchronizing clock signal S15 the frequency of which corresponds to the first and the second recording zones ZN1 and ZN2 in the recording mode. Therefore, the structure of the synchronizing signal processing circuit 10 becomes too complicated.
In order to overcome this, the synchronizing signal processing circuit 10 structured as shown in FIG. 3 is arranged in such a manner that the number of the crystal oscillating circuits is reduced to one.
That is, as shown in FIG. 3, where the same elements as those shown in FIG. 2 are given the same reference numerals, the synchronizing signal processing circuit 10 comprises only one crystal oscillating circuit 21. A frequency signal S21, the frequency of which is f.sub.0 and which is generated due to the oscillating operation of crystal 21X, is transmitted to a first frequency demultiplying circuit 23 of a synthesizer circuit 22.
The frequency demultiplying circuit 23 demultiplies (i.e. divides) the frequency f.sub.0 of the frequency signal S21 at a ratio of 1/K1 before the thus-demultiplied frequency is, as a reference input signal S22, transmitted to a phase comparison circuit 24. In the phase comparison circuit 24, the phase of the reference input signal S22 and the phase of a feedback signal S23 transmitted from a second frequency demultiplying circuit 25 are subjected to a comparison.
An output signal S24, which denotes the result of the phase comparison transmitted from the phase comparison circuit 24, is converted into a DC level voltage signal S25 by a charge pump circuit 26 so as to be supplied to a voltage control type oscillating circuit (VCO) 27.
Thus, a frequency signal having a frequency of f.sub.01, which corresponds to the DC level voltage signal S25, can be obtained at the output terminal of the voltage control oscillating circuit 27. The thus obtained frequency signal is, as a reference clock signal S26, transmitted to the data synchronizer 14. Furthermore, it is demultiplied by the frequency demultiplying circuit 25 at a frequency demultiplying ratio of 1/K2 so as to be fed back as a feedback signal to the phase comparison circuit 24.
In the structure shown in FIG. 3, the synthesizer circuit 22 serves as a PLL (Phase Locked Loop) circuit. Therefore, when a locked state, in which there is no phase error in the output S24 denoting the result of the phase comparison transmitted from the phase comparison circuit 24, is realized, the frequency f.sub.0 of the frequency signal S21 transmitted from the crystal oscillating circuit 21 and the frequency f.sub.01 of the reference clock signal S26, hold a relationship shown by the following equation in which it is expressed by the demultiplying ratios 1/K1 and 1/K2 of the corresponding frequency demultiplying circuits 23 and 25: ##EQU1##
Therefore, the frequency f.sub.01 of the reference clock signal S26 can be changed by changing the frequency demultiplying ratios 1/K1 and 1/K2 with respect to the frequency f.sub.0 as follows: ##EQU2##
The frequency demultiplying ratios 1/K1 and 1/K2 of the corresponding frequency demultiplying circuits 23 and 25 of the synthesizer circuit 22 can be changed by a zone detection signal S27 by utilizing the above-described relationship. As a result, the frequency f.sub.01 of the reference clock signal S26 can be changed to a frequency which corresponds to the data processing speed in the first and the second recording zones ZN1 and ZN2.
In an actual case where the frequency f.sub.01 of the reference clock signal S26 is made to be 24 MHz when data is recorded to the first recording zone ZN1 and it is desired to be changed to 18 MHz when data is recorded to the second recording zone ZN2, the crystal 21X of an oscillating frequency of 24 MHz is used. As a result, the synthesizer circuit 22 is able to transmit the reference clock signal S26 the frequency f.sub.01 of which is 24 MHz while basing on the frequency signal S21 (f.sub.0 =24 MHz) by establishing the frequency-demultiplying numbers K1 and K2 of the corresponding frequency demultiplying circuits 23 and 25 to be K1=4 and K2=4 when the magnetic head is scanning the first recording zone ZN1.
By respectively changing the frequency-demultiplying numbers K1 and K2 of the frequency demultiplying circuits 23 and 25 in such a manner that K1=4 and K2=3 when the magnetic head is scanning the second recording zone ZN2, the synthesizer circuit 22 is able to transmit the reference signal S26 the frequency f.sub.01 of which is 18 MHz while basing on the frequency signal S21 (f.sub.0 =24 MHz).
As described above, the synchronizing signal processing circuit 10 shown in FIG. 3 must comprise only one crystal oscillating circuit. Therefore, the structure can be further simplified in comparison to the synchronizing signal processing circuit 10 shown in FIG. 2. However, the synthesizer circuit 22 structured by the PLL circuit is individually provided in front of the data synchronizer 14 also structured by the PLL circuit. Therefore, the overall structure cannot be satisfactorily simplified.